1. Field of the Invention
The present invention relates to a semiconductor device and a method of manufacturing a semiconductor device.
2. Related Background Art
Semiconductor storage devices including DRAMs are more and more down-scaled in recent years. 1T-1C (1 transistor-1 capacitor) type DRAMs, however, need a certain area for capacitors to secure the storage capacitance of the capacitors. Therefore, 1T-1C DRAMs have a scaling limitation. Further, since 1T-1C DRAMs need capacitors, their manufacturing process is complicated, increasing their manufacturing cost.
To cope with this problem, techniques for forming DRAMs on an S0I (silicon on insulator) substrate have been developed. For example, Japanese Patent Laid Open Publication No. JP-2002-246571 (herein below referred to as Patent Document 1) discloses a DRAM comprising FBCs (Floating Body Cells). The FBC is a memory cell composed of one transistor using an SOI substrate.
The FBC is formed as a MOS transistor on an SOI substrate. Its SOI layer includes a source region, drain region and body region. The body region confined between the source region and the drain region is electrically floating.
The drain current varies with the number of holes in the body region. Data “1” and data “0” can be distinguished by the grade of change of the drain current. That is, by controlling the number of holes accumulated in the body region, the FBC can store data. For example, when more holes exist in the body region, the FBC identifies the data as “1”. When fewer holes exist in the body region, the FBC identifies the data as “0”. In this type of the FBC, in general, the larger the capacitance between the body region and a fixed potential element such as a support substrate, the data retention time is longer, and the function yield is better.
The FBC described in Patent Document 1 increases the capacitance between the body region and the support substrate by using an SOI substrate having a thin buried oxide film (herein below referred as BOX layer).
However, simply thinning the BOX layer invites an increase of the parasitic capacitance between the SOI layer region and the support substrate in peripheral circuits and logic circuits. Increase of the parasitic capacitance decreases the speed of peripheral circuits and logic circuits, and increases their power consumption.
Therefore, the larger the better the capacitance between the body region and the support substrate in the region where an FBC is formed whereas the smaller the better the parasitic capacitance between the SOI layer region and the support substrate in the region where peripheral circuits and logic circuits are formed.